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X90100
Data Sheet February 2, 2005 FN8156.0
NV Electronically Programmable Capacitor
The Intersil X90100 is a non-volatile electronically programmable capacitor. The device is programmed through a simple digital interface. After programming, the chosen setting for the device is retained by internal EEPROM storage whether or not DC power is maintained. There are 32 programmable capacitance values selectable, ranging from 7.5pF to 14.5pF in 0.23pF increments, in single-ended mode. The dielectric is highly stable, and the capacitance exhibits a very low voltage coefficient. It has virtually no dielectric absorbtion and has a very low temperature drift coefficient in differential mode (<50ppm/C). The X90100 is programmed through three digital interface pins, which have Schmitt triggers and pullup resistors to secure code retention. The three pins, INC, U/D, and CS, are identical in operation to other Intersil chips with up/down interface, such as the X9315 5-bit Digitally Controlled Potentiometer (DCP).
Features
* Non-volatile EEPROM storage of programmed trim codes * Power On Recall of capacitance setting * High-Performance Electronically Trimmable Capacitance * Excellent linearity: <0.5 LSB error * Very Simple Digital Interface * Fast adjustments: 5s max incremental change * Eliminates the need for mechanical tuning * Capacitance trimmable from 7.5pF to 14.5pF (singleended mode) * Packages: - MSOP (1.1mm x 3.0mm x 3.0mm)
Applications
* Post-trim of low-cost regenerative receivers * Tunable RF stages * Low-cost, Low temperature drift oscillators
Pinout
X90100 (8 LD MSOP) TOP VIEW
INC U/D Vss Cp 1 2 3 4 8 7 6 5 VCC CS N/C Cm
* Garage door openers * Keyless entry * Industrial wireless control * Capacitive sensor trimming * RFID tags
Ordering Information
ORDERING NUMBER X90100M8I CTOTAL 7.5pF to 14.5pF, Single Ended PACKAGE 8 Ld MSOP 8 Ld MSOP Tape and Reel TEMP RANGE (C) -40 to +85 -40 to +85
X90100M8IT1 7.5pF to 14.5pF, Single Ended
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X90100 Block Diagram
Cm 1*CU 2*CU Cp
CPAD
CPAD
4*CU 8*CU 16*CU VSS
U/D INC Logic and E2 CS
VCC
Power On Reset
Pin Descriptions
MSOP 1 2 3 4 SYMBOL INC U/D VSS Cp BRIEF DESCRIPTION Increment (INC). The INC input is negative-edge triggered. Toggling INC will move the capacitance value and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Up/Down (U/D). The U/D input controls the direction of the trimmed capacitor value and whether the counter is incremented or decremented. Ground. Cp. The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical trimmable capacitor. The minimum dc voltage is VSS and the maximum is VCC. The value of capacitance across the terminals is determined by digital inputs INC, U/D, and CS. Cm. The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical trimmable capacitor. The minimum dc voltage is VSS and the maximum is VCC. The value of capacitance across the terminals is determined by digital inputs INC, U/D, and CS. Not Connected. Must be floating. Chip Select (CS). The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X90100 will be placed in the low power standby mode until the device is selected once again. Positive Supply Voltage.
5
Cm
6 7
N/C CS
8
VCC
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FN8156.0 February 2, 2005
X90100
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D, CP, and CM with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V V = |VCP-VCM|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Capacitor Specifications
SYMBOL Absolute accuracy VCp VCm C C CTOTAL CTOTAL Q
VCC = +5V, TA = 25C, single ended mode, CM = 0V, unless otherwise stated. TEST CONDITIONS/NOTES MIN TYP (4) 15 0 0 0.23 7 7.5 14.5 f = 315MHz 7 5 0.15 0.15 Differential Mode 2.7 50 5.5 bits lsb lsb ppm/C V VCC VCC MAX UNIT % V V pF pF pF pF
PARAMETER
Cp terminal voltage Cm terminal voltage Capacitance increments Capacitance range Capacitance at Code=0 Capacitance at Code=31 Quality factor(5) Resolution
INL DNL TC1 VCC Notes: (1) (2) (3) (4) (5)
Absolute linearity error(1) Relative linearity error(2) CTOTAL Temperature Coefficient(5) Supply Voltage
Absolute linearity is used to determine actual capacitance versus expected capacitance = C(n)(actual) - C(n) (expected) = 0.15 Ml. Relative linearity is a measure of the error in step size between settings = C(n+1)-[C(n) + Ml] = 0.15 Ml. lsb = least significant bit = CTOT/31. Typical values are for TA = 25C and nominal supply voltage. This parameter is not 100% tested. VCC = 5V, TA = 25C unless otherwise specified. TEST CONDITIONS CS = VIL, U/D = VIL or VIH and INC = 0.4V @ max. tCYC CS = VIH, U/D = VIL or VIH and INC = VIH @ max. tWR CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V VIN = VSS VCC x 0.7 -0.5 VCC = 5V, VIN = VSS, TA = 25C, f = 1MHz MIN TYP (4) 50 250 0.5 -15 VCC + 0.5 VCC x 0.1 10 MAX 100 500 2 UNIT A A A A V V pF
DC Electrical Specifications
SYMBOL ICC1 ICC2 ISB ILI VIH VIL CIN(5)
PARAMETER VCC active current (Increment) VCC active current (Store) (EEPROM Store) Standby supply current CS, INC, U/D input leakage current CS, INC, U/D input HIGH voltage CS, INC, U/D input LOW voltage CS, INC, U/D input capacitance
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FN8156.0 February 2, 2005
X90100
Endurance and Data Retention
PARAMETER Minimum endurance Data retention VCC = 5V, TA = 25C unless otherwise specified MIN 100,000 100 UNIT Data changes per bit Years
AC Conditions of Test
Input pulse levels Input rise and fall times Input reference levels 0V to 3V 10ns 1.5V VCC = 5V, TA = 25C unless otherwise specified. MIN 100 100 100 1 1 1 1 10 1 4 500 5 0.2 5 50 10 5 TYP (4) MAX UNIT ns ns ns s s s s ms s s s s V/ms ms
AC Electrical Specifications
SYMBOL tCl tlD tDI tlL(7) tlH(7) tlC tCPHNS(5) tCPHS(5) tIW tCYC tR, tF(5) tPU(5) tR VCC(5) tWR(5) CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period
PARAMETER
INC Inactive to CS inactive CS Deselect time (NO STORE) CS Deselect time (STORE) INC to CTOTAL change INC cycle time INC input rise and fall time Power up to capacitance stable VCC power-up rate Store cycle
AC Timing
CS tCYC tCI INC tIL tIH tIC
(Store) tCPHS 90% 90% 10% tR
tCPHNS
tID
tDI
tF
U/D tIW CTOTAL MI (6)
Notes: (6) MI in the A.C. timing diagram refers to the minimum incremental change in the CTOTAL output due to a change in the counter value. (7) tIH + tIL 4s
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FN8156.0 February 2, 2005
X90100 Power Up Timing (Digital Inputs Floating, Internal Pullup Action Shown)
VCC = 3.3 or 5.0V tRVCC VCC
CS
INC
U/D
Power Up and Down Requirements
There are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the Cp, Cm pins provided that VCC is always more positive than or equal to VCp, VCm, i.e., VCC VCp, VCm. The VCC ramp rate spec is always in effect.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will move the capacitance value and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. This pin has an active current source pullup.
Powerup Requirements
In order to prevent unwanted tap position changes or an inadvertant store, bring the CS and INC high before or concurrently with the VCC pin. The logic inputs have internal active pullups to provide reliable powerup operation. See powerup timing diagram.
Chip Select (CS)
The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X90100 will be placed in the low power standby mode until the device is selected once again. This pin has active circuit source pullup. N/C - This pin should be left floating.
Pin Configuration
MSOP INC U/D Vss Cp 1 2 3 4 X90100 8 7 6 5 VCC CS N/C (leave floating) Cm
Pin Names
SYMBOL Cp Cm VSS DEFAULT output output supply supply pull up pull up pull up DESCRIPTION Positive capacitor terminal Negative capacitor terminal Ground Positive supply voltage Up/Down control input Increment control input Chip Select control input
Detailed Pin Descriptions
Cp and Cm
The high (Cp) and low (Cm) terminals of the X90100 are equivalent to the fixed terminals of a mechanical trimmable capacitor. The minimum dc voltage is VSS and the maximum is VCC. The value of capacitance across the terminals is determined by digital inputs INC, U/D, and CS.
VCC U/D INC CS
Principles of Operation
There are three sections of the X90100: the input control, counter and decode section; the nonvolatile memory; and the capacitor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on electronic switches connecting internal units to the sum capacitor. Under the proper conditions the contents of the counter can be stored in nonvolatile memory
FN8156.0 February 2, 2005
Up/Down (U/D)
The U/D input controls the direction of the trimmed capacitor value and whether the counter is incremented or decremented. This pin has an active current source pullup.
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X90100
and retained for future use. The capacitor array is comprised of 31 individual capacitors connected in parallel. At one end of each element is an electronic switch that connects it to the sum. The capacitor, when at either end of the range, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the counter changes positions. If the counter is moved several positions, multiple units are connected to the total for tIW (INC to CTOTAL change). The CTOTAL value for the device can temporarily be increased by a significant amount if the counter is moved several positions. When the device is powered-down, the last counter position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the capacitor is set to the value last stored. The system may select the X90100, move the capacitor value and deselect the device without having to store the latest count total in nonvolatile memory. After the count movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new CTOTAL value will be maintained until changed by the system or until a powerup/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments can be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the counter up and down until the proper trim is attained.
Mode Selection
CS INC U/D H L H H X L L L X X X H L Cap Value Up Cap Value Down Store Cap Position Standby Current No Store, Return To Standby Cap Value Up (not recommended) Cap Value Down (not recommended) MODE L L
Instructions and Programming
The INC, U/D and CS inputs control the movement of the capacitor total value. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a five bit counter. The output of this counter is decoded to select one of thirty two capacitor combinations for the capacitor array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH.
Table of Values
Single-Ended Mode Differential Mode
COUT =
Code 31
* 7.0 + 7.5 (pF)
COUT = Code * 0.35 + 1.00 (pF) 0 Code 31
0 Code 31
Cp X90100 Cm
X1 Oscillator Circuit X2 X90100
Cm Cp Cp Cs Oscillator Circuit
Example of a single-ended circuit
Example of a differential mode circuit
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FN8156.0 February 2, 2005
X90100 Packaging Information
8-Lead Miniature Small Outline Gull Wing Package Type M
0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) Typ.
R 0.014 (0.36) 0.118 0.002 (3.00 0.05)
0.030 (0.76) 0.0216 (0.55)
0.036 (0.91) 0.032 (0.81)
7 Typ.
0.0256" Typical 0.040 0.002 (1.02 0.05) 0.008 (0.20) 0.004 (0.10)
0.025" Typical 0.220"
0.007 (0.18) 0.005 (0.13)
0.150 (3.81) Ref. 0.193 (4.90) Ref.
FOOTPRINT
0.020" Typical 8 Places
NOTE: 1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN8156.0 February 2, 2005

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